In today's technological world, performances of electronics devices are improving at a rapid pace, with a rapid increase in their computing power. With this increase, the devices are becoming power hungry, i.e., consuming more power. To save power, a processor in a device may enter in a sleep mode (e.g., low power state) during brief periods of inactivity.
For example, the Advanced Configuration and Power Interface (ACPI) specification (e.g., version 3.0a released on Dec. 30, 2005) co-developed by Hewlett-Packard®, Intel®, Microsoft®, Phoenix®, and Toshiba® defines various power states (e.g., processor power states C0-C3 during normal G0/S0 working state of the device) in ACPI-compatible systems. According to the ACPI specification, C0 state may be the normal execution state of the processor. However, while in C1 state during brief period of inactivity, the processor may not execute instructions, but can return to an executing state almost instantaneously, whereas in C3 state (which is a deeper sleep state compared to C1, and saves more power than C1), the processor's caches may maintain state but ignore any snoops. The processor may take longer time to return to a normal executing state (C0) from the C3 state as compared to returning from C1 state. Variations on the each of the states, including the C3 state (e.g., deep sleep, deeper sleep, etc.), that may differ in how deep the processor sleeps (i.e., what functionalities of the processor is disabled to save power) and how long it takes to wake up, is also possible.
Conventional power management, including those defined by the ACPI standard, may be performed based on heuristics collected on the processor and guidance given by the operating system, and a power management algorithm may look at past processor activities to predict future activity. For example, the operating system may look at the central processing unit utilization to provide this guidance. Based on these factors, the processor may enter into one of a plurality of sleep states. Although a processor may intermittently enter into a low power state, other platform components with a longer wake-up time may not usually enter into any such low power state to ensure better performance.
FIG. 1 is an exemplary graphical representation of a total power consumption of a platform (line A) of a prior art computing system and the power consumption of its prior art processor (line B) across a workload consisting of periods of activities while running applications followed by inactivity (idle state). Referring to FIG. 1, the processor may scale its power from up to 20 Watts (W) during brief activity periods to almost 1 W when idle. While the processor is idle, the platform may still have a ˜9 W idle power floor, of which less than 1 W may be due to the processor. That is, the rest of the platform components in the computing system may not scale down as well as the processor during idle states. The platform of this exemplary computing device, in idle state, may still consume about 8-10 W of power due to large portions of system resources, with longer latency (i.e., longer time necessary to wake up from a sleep state), being kept powered up to ensure better performance, while the processor may intermittently enter into appropriate sleep states during idle period.